Design a 3 to 8 Decoder Using Verilog Hdl

VLSI: 3-8 Decoder Structural/Gate Level Modelling with Testbench

Verilog Code for 3-8 Decoder Structural/Gate Level Modelling

3-8 Line Decoder

                      
                        
                                                      module decoder3_to_8(                        
                        
                          input x,                        
                        
                          input y,                        
                        
                          input z,                        
                        
                          output d0,                        
                        
                          output d1,                        
                        
                          output d2,                        
                        
                          output d3,                        
                        
                          output d4,                        
                        
                          output d5,                        
                        
                          output d6,                        
                        
                          output d7                        
                        
                              );                        
                        
                                                      and(d0,xn,yn,zn),(d1,xn,yn,z),(d2,xn,y,zn),(d3,xn,y,z),(d4,x,yn,zn),(d5,x,yn,z),(d6,x,y,zn),(d7,x,y,z);                        
                        
                                                      not(xn,x),(yn,y),(zn,z);                        
                        
                          endmodule                        
                      
                      
                        //Testbench code for 3-8 Decoder Structural/Gate Level Modelling                      
                      
                        
                                                      initial begin                        
                        
                                                      // Initialize Inputs                                                  
                        
                          x = 0;y = 0;z = 0;                        
                        
                                                      // Wait 100 ns for global reset to finish                                                  
                        
                          #100;                        
                        
                                                      // Add stimulus here                                                  
                        
                          #100;x = 0;y = 0;z = 1;                        
                        
                          #100;x = 0;y = 1;z = 0;                        
                        
                          #100;x = 0;y = 1;z = 1;                        
                        
                          #100;x = 1;y = 0;z = 0;                        
                        
                          #100;x = 1;y = 0;z = 1;                        
                        
                          #100;x = 1;y = 1;z = 0;                        
                        
                          #100;x = 1;y = 1;z = 1;                        
                      
                    

Output:

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Design a 3 to 8 Decoder Using Verilog Hdl

Source: https://space-inst.blogspot.com/2020/05/vlsi-3-8-decoder-structuralgate-level.html

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